Stable clocks such as crystal oscillators have been used to generate a sequence of timing signals of variable signal-to-signal interval by programming digital counters to trigger the timing signals at predetermined counts of the clock. Although tapped delay lines having resolution (e.g., 1 nanosecond) higher than that (e.g., 16 ns) of the clock have been used to additionally delay signals relative to the start of the sequence, timing signal interval resolution has in such systems been limited by the clock resolution, with the timing signal period equal to the crystal oscillator period or an integer multiple thereof.
In St. Clair U.S. Pat. No. 4,231,104, desired period values that were not even multiples of the crystal period were obtained by dividing the desired period into a number of crystal periods plus a remainder and a residue value, which was added by a delay line. The remainder was simply the remainder of dividing the desired period by the crystal period (e.g., 2 ns remainder for dividing a 50 ns desired period by a 16 ns clock period). The residue values accounted for the fact that subsequent output pulses were not beginning at a clock signal. (E.g., if the first 50 ns period output appears 2 ns after a clock signal, the next output will have this 2 ns residue in addition to the 2 ns remainder, and will appear 4 ns after a clock signal, in order to be 50 ns after the preceding output..)..!..Iadd..) .Iaddend.A plurality of timing edge generators, employing further delay lines, were driven by these desired period output pulses plus delayed clock signals, obtained by passing clock signals through a delay line delayed by the residue value. The circuitry employing the timing edge generators thus had both the crystal clock signals and asychronous delayed clock signals distributed through it.
In some other timing signal generators, desired periods that are other than integer multiples of a crystal oscillator period are provided by splitting the clock signals into plural phases, and programmably selecting signals from a particular phase to trigger an output (e.g., a 4 ns clock spit into four phases to obtain 1 ns resolution...).!..Iadd.). .Iaddend.